Test Data Compression for System-on-chip using Flexible Runs-aware PRL Coding

This paper presents a flexible runs-aware PRL coding method whose coding algorithm is simple and easy to implement. The internal 2-PRL coding iteratively codes 2 runs of compatible or inversely compatible patterns inside a single segment. The external N-PRL coding iteratively codes flexible runs of compatible or inversely compatible segments across multiple segments. The decoder architecture is concise. The benchmark circuits verify the flexible runs-aware PRL coding method, the experimental results show it obtains higher compression ratio and shorter test application time.